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173
2570N–AVR–05/11
ATmega325/3250/645/6450
Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 20-7. For Double Speed mode the first low level must be delayed to
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
20.8.3
Asynchronous Operational Range
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 20-2) base frequency, the Receiver will not be able to synchronize the frames to the start
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
Sum of character size and parity size (D = 5 to 10 bit)
S
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
S
F
First sample number used for majority voting. S
F = 8 for normal speed and SF = 4
for Double Speed mode.
S
M
Middle sample number used for majority voting. S
M = 9 for normal speed and
S
M = 5 for Double Speed mode.
R
slow
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. R
fast is the ratio of the fastest incoming data rate that can be
accepted in relation to the receiver baud rate.
Table 20-2 and Table 20-3 list the maximum receiver baud rate error that can be tolerated. Note
that Normal Speed mode has higher toleration of baud rate variations.
12
34
56
7
8
9
10
0/1
STOP 1
123
4
5
6
0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)
Rslow
D 1
+
()S
S 1
–
DS
SF
++
-------------------------------------------
=
Rfast
D 2
+
()S
D 1
+
()SS
M
+
-----------------------------------
=
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